DIGITAL-LOGIC SmartModule Express SMX945 Manual do Utilizador Página 51
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Kontron Compact Computers AG SMX945 Detailed Manual V1.1
51
Signal Description I/O Termination Remarks
PCIE0_RX+ PCI Express channel 0
PCIE0_RX- Receive Input differential pair I PCIE Spec. 1.0A
PCIE0_TX+ PCI Express channel 0
PCIE0_TX- Transmit Output differential pair O PCIE Spec. 1.0A
PCIE1_RX+ PCI Express channel 1
PCIE1_RX- Receive Input differential pair I PCIE Spec. 1.0A
PCIE1_TX+ PCI Express channel 1
PCIE1_TX- Transmit Output differential pair O PCIE Spec. 1.0A
PCIE2_RX+ PCI Express channel 2
PCIE2_RX- Receive Input differential pair I PCIE Spec. 1.0A
PCIE2_TX+ PCI Express channel 2
PCIE2_TX- Transmit Output differential pair O PCIE Spec. 1.0A
PCIE3_RX+ PCI Express channel 3
PCIE3_RX- Receive Input differential pair I PCIE Spec. 1.0A
PCIE3_TX+ PCI Express channel 3
PCIE3_TX- Transmit Output differential pair O PCIE Spec. 1.0A
PCIE_CLK_REF+ PCI Express Reference Clock 0 PCIE PD 50Ohm Spec 1.0a
PCIE_CLK_REF- or Lanes 0 to 3
PCE_WAKE# PCI Express Wake Event I 3.3VSB
PU 1K 3.3VSB
Sideband wake signal asserted
by components requesting wakeup
PCIE_Reset# Reset# O 3.3V Generated from the PCI_Reset#,
coming from Pin C23, buffered
with a 74HC08 (3.3V).
The insertion losses previously allowed for the slot card and slot card connector are re-allocated for use on
the carrier board, allowing longer carrier board trace lengths and more carrier board design flexibility. The
module and COM Express™ connector-loss budgets remain the same.
- SmartModule Express 1
- SMX945 / SMX945B 1
- COPYRIGHT 2
- REVISION HISTORY: 2
- Table of Contents 3
- 1. PREFACE 5
- 1.5. Recycling Information 6
- 1.6. Technical Support 6
- 1.8. Explanation of Symbols 7
- 1.10. For Your Safety 9
- 1.11. RoHS Commitment 9
- 1.11.3. WEEE Application 10
- 1.12. Swiss Quality 11
- Systems 11
- 2. OVERVIEW 12
- 2.2. Unique Features 13
- 2.3. Standards 13
- 2.4. Block Diagram 14
- 2.5. Specifications 15
- 2.7. Product Pictures: 18
- 2.8. Thermoscan 19
- FUNCTIONAL DESCRIPTION 20
- 3.1. Power Input 20
- 3.2. Watchdog Control 21
- 3.3. BIOS 22
- 3.4. CMOS RAM Map 23
- 3.5. System Memory Map 23
- 3.6. Graphics Controller 24
- ESCRIPTION OF THE JUMPERS 24
- 5. LED CRITERIA: 25
- 6.1. Mechanical Assembly 26
- Attention! 27
- 6.2. Assembly / Disassembly 33
- 6.2.2. SODIMM-DDR2 RAM 34
- 6.4. Signal Loss 43
- Point-to-point, match 44
- TX must be AC coupled 44
- 6.5.2. Layout Rules 45
- 6.6. Signal Descriptions 47
- Note 52
- 6.8. Thermal Specifications 55
- 7.1. Video Signals 56
- 7.2. IDE Signals 57
- 7.3. AC97 Audio Signals 58
- 7.4. USB2 Signal 59
- 7.5. LAN Signals 60
- 7.6. Power Planes 61
- 8. DETAILED SPECIFICATIONS 62
- 8.2.1. Thermal Management 63
- 8.2.3. Implementation 64
- 8.4. PCI Resources 66
- 9. CORE BIOS 67
- 10. SCHEMATICS 67
- 11. INDEX 85
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